The present invention relates generally to computer systems. More particularly, the invention relates to a mechanism for updating cache memory tag data.
A current trend in the design of scalable multiprocessor computer systems is to utilize a general interconnect network to connect clusters of processors. This particular design is advantageous over shared bus configurations of multiprocessors which were limited to the bandwidth of the bus. In such multiprocessor computer systems, each processor is associated with a memory that is accessible by other processors in the same cluster and by other clusters. Since the clusters are not connected by a shared bus, a snoopy bus protocol is not sufficient to maintain cache coherency. Instead, a directory-based coherency protocol is used to maintain cache coherency for data that is shared by the other clusters in the multiprocessor system.
A directory-based coherency protocol associates tags with each memory line. The tag can contain state information that indicates the ownership or usage of the memory line. The state information provides a means to track the data that is shared. Examples of the usage information can be whether the memory line is cached exclusively in a particular processor""s cache, whether the memory line is shared by a number of processors, or whether the memory line is currently cached by any processor.
In order to maintain cache coherency, the tag is updated after each memory access. Typically, a memory controller is used to control access to the memory banks. For a read operation, the memory controller requests a memory line from the memory bank. When the memory line is retrieved from the memory bank, the memory controller then writes back the memory line with the updated tag to the memory bank. Although this method ensures cache coherency, it consumes a considerable amount of the memory bank""s time in writing back the memory line with the updated tag information. Accordingly, there is a need to overcome this shortcoming.
In summary, the technology of the present invention pertains to an apparatus and method for performing speculative cache tag directory updates. In an embodiment of the present invention, a multiprocessor computer system is used where the system memory image is distributed amongst several cells and where portions of the system memory can be accessed from within a cell and/or between cells. A directory-based coherency protocol is used where each memory line has an associated tag that includes state information that identifies the owner or sharers of that memory line. The state information provides a means to track the data or memory lines that are shared within the multiprocessor system in order to maintain the system memory in a coherent manner.
A tag update unit is employed to update the tags whenever a word is read from a memory bank. A memory line that is read from a memory bank is simultaneously read back to the memory controller while the tag update unit calculates an updated tag and its corresponding ECC data. The updated word is then written back to the memory bank from the tag update unit.
The use of the tag update unit to calculate the updated tag data and to write back the word to the memory bank improves the overall system performance by reducing the memory bank busy time and the memory bus traffic. The memory bank busy time is reduced by overlapping the transmission of the word to the memory controller while the tag update unit calculates the updated tag data and writes the word to the memory bank.
The tag update methodology assumes that the word read from the memory bank does not contain any single or multi-bit errors and hence, speculatively performs the tag updates. The memory controller will receive the entire memory line and check the ECC portion of the memory line. If the memory controller detects a correctable error or an error in the updated tag, or if the memory controller incorrectly speculated the coherency for the tag, the memory controller will perform a subsequent memory access to overwrite the memory line having the corrupted data and/or tags. This subsequent memory operation will be performed before another access is made to the memory bank in order to prevent an access to the corrupted memory line. However, such errors are infrequent and the need to perform the subsequent write back is seldom.